Chemical mechanical polishing (“CMP”) is commonly used in current advanced semiconductor processing. In CMP a rotating pad receives abrasive slurry. The pad is mounted on a platen and typically oriented in a face up arrangement. A wafer carrier is moved downward towards the pad. The wafer carrier may rotate about a central axis and may oscillate. A vacuum or electrostatic force may be used to mount a semiconductor wafer is to the carrier. The wafer carrier is positioned so that the face of the semiconductor wafer contacts the polishing pad and the slurry. The wafer and carrier may also rotate and oscillate during the polishing process. The wafer may have a dielectric layer that requires planarization, for example. In other process steps, for example for damascene metal fabrication, CMP can be used to remove excess metal and planarize the upper surface of plated metal conductors and the surrounding dielectric, to form inlaid metal conductors within the dielectric layers. By abrasively polishing the surface of the semiconductor wafer, asperities in layers can be removed to planarize the layer. Excess material may be removed as well.
During CMP processing of a surface, particles are sometimes generated. If a hard particle gets trapped on the wafer surface between the wafer and the CMP polishing pad, wafer scratching can occur. The scratches can cause defects in the integrated circuit devices that are being manufactured on the wafer and result in a loss of these devices. The wafer scratches are often not detected until the wafer processing reaches a later stage where some scan or visual inspection is done. The scratch detection may happen after many more processing steps are performed. Currently there is no mechanism for detecting wafer scratches as they occur during the CMP process. This leads to many wasted steps and loss of materials and time.
A continuing need thus exists for methods and apparatus for detecting wafer scratching problems or other errors in CMP processes without the disadvantages currently experienced using known methods.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.